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19-0464; Rev 3; 5/09
+2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs
General Description
The MAX148/MAX149 10-bit data-acquisition systems combine an 8-channel multiplexer, high-bandwidth track/hold, and serial interface with high conversion speed and low power consumption. They operate from a single +2.7V to +5.25V supply, and sample to 133ksps. Both devices' analog inputs are software configurable for unipolar/bipolar and single-ended/differential operation. The 4-wire serial interface connects directly to SPIK/ QSPIK and MICROWIREK devices without external logic. A serial-strobe output allows direct connection to TMS320-family digital signal processors. The MAX148/ MAX149 use either the internal clock or an external serial-interface clock to perform successive-approximation analog-to-digital conversions. The MAX149 has an internal 2.5V reference, while the MAX148 requires an external reference. Both parts have a reference-buffer amplifier with a Q1.5% voltageadjustment range. These devices provide a hard-wired SHDN pin and a software-selectable power-down, and can be programmed to automatically shut down at the end of a conversion. Accessing the serial interface automatically powers up the MAX148/MAX149, and the quick turn-on time allows them to be shut down between all conversions. This technique can cut supply current to under 60FA at reduced sampling rates. The MAX148/MAX149 are available in a 20-pin DIP and a 20-pin SSOP. For 4-channel versions of these devices, see the MAX1248/MAX1249 data sheet. Inputs
S Single-Supply Operation: +2.7V to +5.25V S Internal 2.5V Reference (MAX149) S Low Power: 1.2mA (133ksps, 3V Supply)
Features
S 8-Channel Single-Ended or 4-Channel Differential
MAX148/MAX149
54A (1ksps, 3V Supply) 1A (Power-Down Mode)
S SPI/QSPI/MICROWIRE/TMS320-Compatible 4-Wire
Serial Interface
S Software-Configurable Unipolar or Bipolar Inputs S 20-Pin DIP/SSOP Packages
Ordering Information
PART MAX148ACPP MAX148BCPP MAX148ACAP MAX148BCAP TEMP RANGE 0C to +70C 0C to +70C 0C to +70C 0C to +70C PINPACKAGE 20 Plastic DIP 20 Plastic DIP 20 SSOP 20 SSOP INL (LSB) 1/2 1 1/2 1
Ordering Information continued at end of data sheet. Contact factory for availability of alternate surface-mount package. Specify lead-free by placing + by the part number when ordering.
*Contact factory for availability of CERDIP package, and for processing to MIL-STD-883B. Not available in lead-free.
Typical Operating Circuit
+3V CH0 O TO +2.5V ANALOG INPUTS CH7 VREF 4.7FF READJ VDD 0.1FF DGND MAX149 VDD
Applications
Portable Data Logging Data Acquisition Medical Instruments Battery-Powered Instruments Pen Digitizers Process Control
Pin Configuration appears at end of data sheet.
AGND COM CS SCLK DIN DOUT SSTRB SHDN CPU I/O SCK (SK) MOSI (SO) MISO (SI) VSS
0.01FF
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
+2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs MAX148/MAX149
ABSOLUTE MAXIMUM RATINGS
VDD to AGND, DGND..............................................-0.3V to +6V AGND to DGND ...................................................-0.3V to +0.3V CH0-CH7, COM to AGND, DGND........... -0.3V to (VDD + 0.3V) VREF, REFADJ to AGND ...........................-0.3V to (VDD + 0.3V) Digital Inputs to DGND ...........................................-0.3V to +6V Digital Outputs to DGND .......................... -0.3V to (VDD + 0.3V) Digital Output Sink Current ................................................25mA Continuous Power Dissipation (TA = +70NC) Plastic DIP (derate 11.11mW/NC above +70NC) ..........889mW SSOP (derate 8.00mW/NC above +70NC) ....................640mW CERDIP (derate 11.11mW/NC above +70NC) ..............889mW Operating Temperature Ranges MAX148_C_P/MAX149_C_P .............................. 0NC to +70NC MAX148_E_P/MAX149_E_P ............................ -40NC to +85NC MAX148_MJP/MAX149_MJP ........................ -55NC to +125NC MAX149BMAP ............................................... -55NC to +125NC Storage Temperature Range............................ -60NC to +150NC Lead Temperature (soldering, 10s) ................................+300NC
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +5.25V; COM = 0; fSCLK = 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX149--4.7FF capacitor at VREF pin; MAX148--external reference, VREF = 2.500V applied to VREF pin; TA = TMIN to TMAX, unless otherwise noted.) PARAMETER DC ACCURACY (Note 1) Resolution Relative Accuracy (Note 2) Differential Nonlinearity Offset Error Gain Error (Note 3) Gain Temperature Coefficient Channel-to-Channel Offset Matching Signal-to-Noise + Distortion Noise Total Harmonic Distortion Spurious-Free Dynamic Range Channel-to-Channel Crosstalk Small-Signal Bandwidth Full-Power Bandwidth CONVERSION RATE Internal clock, SHDN = unconnected Conversion Time (Note 5) tCONV Internal clock, SHDN = VDD External clock = 2MHz, 12 clocks/ conversion 5.5 35 6 1.5 30 < 50 s ns ps 7.5 65 s INL DNL MAX14_A MAX14_B No missing codes over temperature MAX14_A MAX14_B MAX14_A MAX14_B 0.25 0.05 0.15 0.15 10 0.5 1.0 1 1 2 1 2 Bits LSB LSB LSB LSB ppm/C LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC SPECIFICATIONS (10kHz Sine-Wave Input, 0 to 2.500VP-P, 133ksps, 2.0MHz External Clock, Bipolar Input Mode) SINAD THD SFDR 65kHz, 2.500VP-P (Note 4) -3dB rolloff Up to the 5th harmonic 66 -70 70 -75 2.25 1.0 dB dB dB dB MHz MHz
Track/Hold Acquisition Time Aperture Delay Aperture Jitter
tACQ
2
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+2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.25V; COM = 0; fSCLK = 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX149--4.7FF capacitor at VREF pin; MAX148--external reference, VREF = 2.500V applied to VREF pin; TA = TMIN to TMAX, unless otherwise noted.) PARAMETER CONVERSION RATE (continued) Internal Clock Frequency External Clock Frequency ANALOG/COM INPUTS Input Voltage Range, SingleEnded and Differential (Note 6) Multiplexer Leakage Current Input Capacitance INTERNAL REFERENCE (MAX149 Only, Reference Buffer Enabled) VREF Output Voltage VREF Short-Circuit Current VREF Temperature Coefficient Load Regulation (Note 8) Capacitive Bypass at VREF Capacitive Bypass at REFADJ REFADJ Adjustment Range EXTERNAL REFERENCE AT VREF (Buffer Disabled) VREF Input Voltage Range (Note 9) VREF Input Current VREF Input Resistance Shutdown VREF Input Current REFADJ Buffer-Disable Threshold EXTERNAL REFERENCE AT REFADJ Capacitive Bypass at VREF Reference Buffer Gain REFADJ Input Current Internal compensation mode External compensation mode MAX149 MAX148 MAX149 MAX148 0 4.7 2.06 2.00 50 10 F V/V A VDD 0.5 VREF = 2.500V 18 1.0 100 25 0.01 10 VDD + 50mV 150 V A k A V MAX149 0 to 0.2mA output load Internal compensation mode External compensation mode 0 4.7 0.01 1.5 30 0.35 TA = +25C (Note 7) 2.470 2.500 2.530 30 V mA ppm/C mV F F % Unipolar, COM = 0 Bipolar, COM = VREF/2 On/off leakage current, VCH_ = 0 or VDD 0.01 16 0 to VREF VREF/2 1 V A pF SHDN = unconnected SHDN = VDD 0.1 Data transfer only 1 1.8 0.225 2.0 2.0 MHz MHz SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX148/MAX149
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3
+2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs MAX148/MAX149
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.25V; COM = 0; fSCLK = 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps); MAX149--4.7FF capacitor at VREF pin; MAX148--external reference, VREF = 2.500V applied to VREF pin; TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL VDD 3.6V VDD > 3.6V CONDITIONS MIN 2.0 3.0 0.8 0.2 VIN = 0 or VDD (Note 10) VDD 0.4 1.1 VDD 1.1 0.4 SHDN = 0 or VDD SHDN = unconnected SHDN = unconnected VDD/2 100 4.0 0.01 1 15 TYP MAX UNITS DIGITAL INPUTS (DIN, SCLK, CS, SHDN) DIN, SCLK, CS Input High Voltage DIN, SCLK, CS Input Low Voltage DIN, SCLK, CS Input Hysteresis DIN, SCLK, CS Input Leakage DIN, SCLK, CS Input Capacitance SHDN Input High Voltage SHDN Input Mid Voltage SHDN Input Low Voltage SHDN Input Current SHDN Voltage, Unconnected SHDN Maximum Allowed Leakage, Mid Input DIGITAL OUTPUTS (DOUT, SSTRB) Output-Voltage Low Output-Voltage High Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS Positive Supply Voltage VDD Operating mode, full-scale VDD = 5.25V input (Note 11) VDD = 3.6V Positive Supply Current IDD Full power-down Fast power-down (MAX149) Supply Rejection (Note 12) PSR Full-scale input, external reference = 2.500V, VDD = 2.7V to 5.25V VDD = 5.25V VDD = 3.6V 2.70 1.6 1.2 3.5 1.2 30 0.3 5.25 3.0 2.0 15 10 70 mV A V mA VOL VOH IL COUT ISINK = 5mA ISINK = 16mA ISOURCE = 0.5mA CS = VDD CS = VDD (Note 10) VDD 0.5 0.01 10 15 0.4 0.8 V V A pF VIH VIL VHYST IIN CIN VSH VSM VSL IS VFLT V V V A pF V V V A V nA
4
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+2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs
TIMING CHARACTERISTICS
(VDD = +2.7V to +5.25V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER Acquisition Time DIN to SCLK Setup DIN to SCLK Hold SCLK Fall to Output Data Valid CS Fall to Output Enable CS Rise to Output Disable CS to SCLK Rise Setup CS to SCLK Rise Hold SCLK Pulse Width High SCLK Pulse Width Low SCLK Fall to SSTRB CS Fall to SSTRB Output Enable CS Rise to SSTRB Output Disable SSTRB Rise to SCLK Rise SYMBOL tACQ tDS tDH tDO tDV tTR tCSS tCSH tCH tCL tSSTRB tSDV tSTR tSCK Figure 1 External clock mode only, Figure 1 External clock mode only, Figure 2 Internal clock mode only (Note 7) 0 Figure 1 Figure 1 Figure 2 100 0 200 200 240 240 240 MAX14_ _C/E MAX14_ _M CONDITIONS MIN 1.5 100 0 20 20 200 240 240 240 TYP MAX UNITS s ns ns ns ns ns ns ns ns ns ns ns ns ns
MAX148/MAX149
5
Note 1: Tested at VDD = 2.7V; COM = 0; unipolar single-ended input mode. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated. Note 3: MAX149--internal reference, offset nulled; MAX148--external reference (VREF = +2.500V), offset nulled. Note 4: Ground "on" channel; sine wave applied to all "off" channels. Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. Note 6: The common-mode range for the analog inputs is from AGND to VDD. Note 7: Sample tested to 0.1% AQL. Note 8: External load should not change during conversion for specified accuracy. Note 9: ADC performance is limited by the converter's noise floor, typically 300FVP-P. Note 10: Guaranteed by design. Not subject to production testing. Note 11: The MAX148 typically draws 400FA less than the values shown. Note 12: Measured as |VFS(2.7V) - VFS(5.25V)|.
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+2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs MAX148/MAX149
Typical Operating Characteristics
(VDD = 3.0V, VREF = 2.500V, fSCLK = 2.0MHz, CLOAD = 20pF, TA = +25NC, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. CODE
MAX148-MAX149 toc01
INTEGRAL NONLINEARITY vs. SUPPLY VOLTAGE
MAX148-MAX149 toc02
INTEGRAL NONLINEARITY vs. TEMPERATURE
VDD = 2.7V
MAX148-MAX149 toc03
0.125 0.100 MAX149 INL (LSB) 0.075 0.050 0.025
0.125 0.100 0.075 0.050
0.10 0.05 INL (LSB)
0
-0.05 -0.10 0 256 512 CODE 768 1024 0 2.25 2.75
MAX148
INL (LSB)
MAX149
MAX148 0.025 0
3.25 3.75 4.25 SUPPLY VOLTAGE (V)
4.75
5.25
-60
-20
20 60 TEMPERATURE (NC)
100
140
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX148-MAX149 toc04
SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE
FULL POWER-DOWN SHUTDOWN SUPPLY CURRENT (FA)
MAX148-MAX149 toc05
MAX149 INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE
INTERNAL REFERENCE VOLTAGE (V)
MAX148-MAX149 toc06
2.00 1.75 SUPPLY CURRENT (mA) 1.50 1.25 1.00 0.75 0.50
RL = J CODE = 1010101000
3.0 2.5 2.0 1.5 1.0 0.5 0
2.5020 2.5015 2.5010 2.5005 2.5000 2.4995 2.4990
CLOAD = 50pF
MAX149
CLOAD = 20pF
MAX148 2.25 2.75 3.25 3.75 4.25 SUPPLY VOLTAGE (V) 4.75 5.25
2.25
2.75
3.25 3.75 4.25 SUPPLY VOLTAGE (V)
4.75
5.25
2.25
2.75
3.25 3.75 4.25 SUPPLY VOLTAGE (V)
4.75
5.25
SUPPLY CURRENT vs. TEMPERATURE
MAX148-MAX149 toc07
SHUTDOWN CURRENT vs. TEMPERATURE
MAX148-MAX149 toc08
MAX149 INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE
VDD = 5.25V VDD = 3.6V VDD = 2.7V INTERNAL REFERENCE VOLTAGE (V) 2.500 2.499 2.498 2.497 2.496 2.495 2.494
MAX148-MAX149 toc09
1.3 1.2 SUPPLY CURRENT (mA) 1.1 1.0 MAX148 0.9 0.8 -60 RL0AD = J CODE = 1010101000 -20 20 60 TEMPERATURE (NC) 100 MAX149
2.0 1.6 1.2 0.8 0.4 0 -60 -20 20 60 TEMPERATURE (NC) 100
2.501
140
SHUTDOWN CURRENT (mA)
140
-60
-20
20 60 TEMPERATURE (NC)
100
140
6
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+2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs
Pin Description
PIN 1-8 9 NAME CH0-CH7 COM Sampling Analog Inputs Ground Reference for Analog Inputs. COM sets zero-code voltage in single-ended mode. Must be stable to 0.5 LSB. Three-Level Shutdown Input. Pulling SHDN low shuts the MAX148/MAX149 down; otherwise, they are fully operational. Pulling SHDN high puts the reference-buffer amplifier in internal compensation mode. Leaving SHDN unconnected puts the reference-buffer amplifier in external compensation mode. Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion. In internal reference mode (MAX149 only), the reference buffer provides a 2.500V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to VDD. Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to VDD. Analog Ground Digital Ground Serial-Data Output. Data is clocked out at SCLK's falling edge. High impedance when CS is high. Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX148/MAX149 begin the A/D conversion, and goes high when the conversion is finished. In external clock mode, SSTRB pulses high for one clock period before the MSB decision. High impedance when CS is high (external clock mode). Serial-Data Input. Data is clocked in at SCLK's rising edge. Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT is high impedance. Serial-Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets the conversion speed (duty cycle must be 40% to 60%). Positive Supply Voltage FUNCTION
MAX148/MAX149
10
SHDN
11
VREF
12 13 14 15
REFADJ AGND DGND DOUT
16
SSTRB
17 18 19 20
DIN CS SCLK VDD
VDD 6kI DOUT 6kI DGND a) HIGH-Z TO VOH AND VOL TO VOH b) HIGH-Z TO VOL AND VOH TO VOL CLOAD 50pF DOUT CLOAD 50pF DGND
VDD 6kI DOUT 6kI DGND a) VOH TO HIGH-Z CLOAD 50pF DOUT CLOAD 50pF DGND
b) VOL TO HIGH-Z
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disable Time 7
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+2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs MAX148/MAX149
Detailed Description
The MAX148/MAX149 analog-to-digital converters (ADCs) use a successive-approximation conversion technique and input track/hold (T/H) circuitry to convert an analog signal to a 10-bit digital output. A flexible serial interface provides easy interface to microprocessors (FPs). Figure 3 is a block diagram of the MAX148/ MAX149. The sampling architecture of the ADC's analog comparator is illustrated in the equivalent input circuit (Figure 4). In single-ended mode, IN+ is internally switched to CH0-CH7, and IN- is switched to COM. In differential mode, IN+ and IN- are selected from the following pairs: CH0/CH1, CH2/CH3, CH4/CH5, and CH6/CH7. Configure the channels with Tables 2 and 3. In differential mode, IN- and IN+ are internally switched to either of the analog inputs. This configuration is pseudo-differential to the effect that only the signal at IN+ is sampled. The return side (IN-) must remain stable within Q0.5 LSB (Q0.1 LSB for best results) with respect to AGND during a conversion. To accomplish this, connect a 0.1FF capacitor from IN- (the selected analog input) to AGND. During the acquisition interval, the channel selected as the positive input (IN+) charges capacitor CHOLD. The acquisition interval spans three SCLK cycles and ends on the falling SCLK edge after the last bit of the input
18 19 17 10 1 2 3 4 5 6 7 8 9 INPUT SHIFT REGISTER INT CLOCK 15 16 CAPACITIVE DAC VREF INPUT MUX CHOLD + 16pF CSWITCH TRACK T/H SWITCH RIN 9k HOLD AT THE SAMPLING INSTANT, THE MUX INPUT SWITCHES FROM THE SELECTED IN+ CHANNEL TO THE SELECTED IN- CHANNEL. COMPARATOR ZERO
control word has been entered. At the end of the acquisition interval, the T/H switch opens, retaining charge on CHOLD as a sample of the signal at IN+. The conversion interval begins with the input multiplexer switching CHOLD from the positive input (IN+) to the negative input (IN-). In single-ended mode, IN- is simply COM. This unbalances node ZERO at the comparator's input. The capacitive DAC adjusts during the remainder of the conversion cycle to restore node ZERO to 0 within the limits of 10-bit resolution. This action is equivalent to transferring a 16pF x [(VIN+) - (VIN-)] charge from CHOLD to the binary-weighted capacitive DAC, which in turn forms a digital representation of the analog input signal. The T/H enters its tracking mode on the falling clock edge after the fifth bit of the 8-bit control word has been shifted in. It enters its hold mode on the falling clock edge after the eighth bit of the control word has been shifted in. If the converter is set up for single-ended inputs, IN- is connected to COM, and the converter samples the "+" input. If the converter is set up for differential inputs, IN- connects to the "-" input, and the difference of |IN+ - IN-| is sampled. At the end of the conversion, the positive input connects back to IN+, and CHOLD charges to the input signal. The time required for the T/H to acquire an input signal is a function of how quickly its input capacitance is charged. If the input signal's source impedance is high, the acquisition time lengthens, and more time must be
Pseudo-Differential Input
Track/Hold
CS SCLK DIN SHDN CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
CONTROL LOGIC
OUTPUT SHIFT REGISTER ANALOG INPUT MUX T/H CLOCK IN 10+2-BIT SAR ADC OUT REF A 2.06*
DOUT SSTRB
20 14 13
VDD DGND AGND
REFADJ VREF
12 11
+1.21V REFERENCE (MAX149)
20k
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
+2.500V *A 2.00 (MAX148)
MAX148 MAX149
SINGLE-ENDED MODE: IN+ = CH0-CH7, IN- = COM. DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7.
Figure 3. Block Diagram 8
Figure 4. Equivalent Input Circuit
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+2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs MAX148/MAX149
VDD 0.1F DGND AGND MAX148 MAX149 CH7 COM SSTRB CS SCLK +3V 2.5V 1000pF REFADJ DIN DOUT SSTRB SHDN OPTIONAL FOR MAX149, REQUIRED FOR MAX148 *FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX) N.C. +3V 2MHz OSCILLATOR CH1 CH2 CH3 CH4 DOUT* SCLK +3V OSCILLOSCOPE
0 TO +2.500V ANALOG INPUT 0.01F +3V VOUT MAX872 COMP
VREF C1 0.1F
Figure 5. Quick-Look Circuit
allowed between conversions. The acquisition time, tACQ, is the maximum time the device takes to acquire the signal, and is also the minimum time needed for the signal to be acquired. It is calculated by the following equation: tACQ = 7 x (RS + RIN) x 16pF where RIN = 9kI, RS = the source impedance of the input signal, and tACQ is never less than 1.5Fs. Note that source impedances below 4kI do not significantly affect the ADC's AC performance. Higher source impedances can be used if a 0.01FF capacitor is connected to the individual analog inputs. Note that the input capacitor forms an RC filter with the input source impedance, limiting the ADC's signal bandwidth. The ADC's input tracking circuitry has a 2.25MHz small-signal bandwidth, so it is possible to digitize highspeed transient events and measure periodic signals with bandwidths exceeding the ADC's sampling rate by using undersampling techniques. To avoid highfrequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended.
Internal protection diodes, which clamp the analog input to VDD and AGND, allow the channel input pins to swing from AGND - 0.3V to VDD + 0.3V without damage. However, for accurate conversions near full scale, the inputs must not exceed VDD by more than 50mV or be lower than AGND by 50mV. If the analog input exceeds 50mV beyond the supplies, do not forward bias the protection diodes of off channels over 2mA. To quickly evaluate the MAX148/MAX149's analog performance, use the circuit of Figure 5. The MAX148/ MAX149 require a control byte to be written to DIN before each conversion. Tying DIN to +3V feeds in control bytes of $FF (HEX), which trigger single-ended unipolar conversions on CH7 in external clock mode without powering down between conversions. In external clock mode, the SSTRB output pulses high for one clock period before the most significant bit of the conversion result is shifted out of DOUT. Varying the analog input to CH7 will alter the sequence of bits from DOUT. A total of 15 clock cycles is required per conversion. All transitions of the SSTRB and DOUT outputs occur on the falling edge of SCLK.
9
Analog Input Protection
Quick Look
Input Bandwidth
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+2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs MAX148/MAX149
Table 1. Control-Byte Format
BIT 7 (MSB) START BIT 7(MSB) 6 5 4 3 BIT 6 SEL2 NAME START SEL2 SEL1 SEL0 UNI/BIP BIT 5 SEL1 BIT 4 SEL0 BIT 3 UNI/BIP BIT 2 SGL//DIF BIT 1 PD1 BIT 0 (LSB) PD0
DESCRIPTION The first logic "1" bit after CS goes low defines the beginning of the control byte. These three bits select which of the eight channels are used for the conversion (Tables 2 and 3) 1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an analog input signal from 0 to VREF can be converted; in bipolar mode, the signal can range from -VREF/2 to +VREF/2. 1 = single ended, 0 = differential. Selects single-ended or differential conversions. In singleended mode, input signal voltages are referred to COM. In differential mode, the voltage difference between two channels is measured (Tables 2 and 3). Selects clock and power-down modes. PD1 0 PD0 0 1 0 1 Mode Full power-down Fast power-down (MAX149 only) Internal clock mode External clock mode
2 1
SGL/DIF PD1
0(LSB)
PD0
0 1 1
Table 2. Channel Selection in Single-Ended Mode (SGL/DIF = 1)
SEL2 0 1 0 1 0 1 0 1 SEL1 0 0 0 0 1 1 1 1 SEL0 0 0 1 1 0 0 1 1 CH0 + + + + + + + + CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM -
Start a conversion by clocking a control byte into DIN. With CS low, each rising edge on SCLK clocks a bit from DIN into the MAX148/MAX149's internal shift register. After CS falls, the first arriving logic "1" bit defines the control byte's MSB. Until this first "start" bit arrives, any number of logic "0" bits can be clocked into DIN with no effect. Table 1 shows the control-byte format. The MAX148/MAX149 are compatible with SPI/QSPI and MICROWIRE devices. For SPI, select the correct clock
How to Start a Conversion
polarity and sampling edge in the SPI control registers: set CPOL = 0 and CPHA = 0. MICROWIRE, SPI, and QSPI all transmit a byte and receive a byte at the same time. Using the Typical Operating Circuit, the simplest software interface requires only three 8-bit transfers to perform a conversion (one 8-bit transfer to configure the ADC, and two more 8-bit transfers to clock out the conversion result). See Figure 20 for MAX148/ MAX149 QSPI connections.
10
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+2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs
Table 3. Channel Selection in Differential Mode (SGL/DIF = 0)
SEL2 0 0 0 0 1 1 1 1 SEL1 0 0 1 1 0 0 1 1 SEL0 0 1 0 1 0 1 0 1 + + + + CH0 + CH1 + + + CH2 CH3 CH4 CH5 CH6 CH7
MAX148/MAX149
CS tACQ SCLK 1 4 UNI/ SGL/ BIP DIF PD1 8 12 16 20 24
DIN START
SEL2 SEL1 SEL0
PD0
SSTRB
RB1 DOUT ACQUISITION A/D STATE IDLE 1.5Fs (fSCLK = 2MHz) B9 MSB B8 B7
RB2 B6 B5 B4 B3 B2 B1 B0 LSB S1
RB3 S0
FILLED WITH ZEROS
CONVERSION
IDLE
Figure 6. 24-Clock External Clock Mode Conversion Timing (MICROWIRE and SPI-Compatible, QSPI-Compatible with fSCLK P 2MHz)
Simple Software Interface Make sure the CPU's serial interface runs in master mode so the CPU generates the serial clock. Choose a clock frequency from 100kHz to 2MHz. 1) Set up the control byte for external clock mode and call it TB1. TB1 should be of the format: 1XXXXX11 binary, where the Xs denote the particular channel and conversion mode selected. 2) Use a general-purpose I/O line on the CPU to pull CS low. 3) Transmit TB1 and, simultaneously, receive a byte and call it RB1. Ignore RB1. 4) Transmit a byte of all zeros ($00 hex) and, simultaneously, receive byte RB2. 5) Transmit a byte of all zeros ($00 hex) and, simultaneously, receive byte RB3. 6) Pull CS high.
Figure 6 shows the timing for this sequence. Bytes RB2 and RB3 contain the result of the conversion, padded with one leading zero, two sub-LSB bits, and three trailing zeros. The total conversion time is a function of the serial-clock frequency and the amount of idle time between 8-bit transfers. To avoid excessive T/H droop, make sure the total conversion time does not exceed 120Fs. Digital Output In unipolar input mode, the output is straight binary (Figure 17). For bipolar input mode, the output is twos complement (Figure 18). Data is clocked out at the falling edge of SCLK in MSB-first format. The MAX148/MAX149 may use either an external serial clock or the internal clock to perform the successiveapproximation conversion. In both clock modes, the external clock shifts data in and out of the MAX148/MAX149.
11
Clock Modes
______________________________________________________________________________________
+2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs MAX148/MAX149
CS
tCSH SCLK
tCSS
tCL
tCH
tCSH
tDS tDH DIN
tDV DOUT
tDO
tTR
Figure 7. Detailed Serial-Interface Timing
CS
tSDV
tSTR
SSRTB tSSTRB tSSTRB
SCLK
PD0 CLOCKED IN
Figure 8. External Clock Mode SSTRB Detailed Timing
The T/H acquires the input signal as the last three bits of the control byte are clocked into DIN. Bits PD1 and PD0 of the control byte program the clock mode. Figures 7-10 show the timing characteristics common to both modes. External Clock In external clock mode, the external clock not only shifts data in and out, but it also drives the analog-to-digital conversion steps. SSTRB pulses high for one clock period after the last bit of the control byte. Successive- approximation bit decisions are made and appear at DOUT on each of the next 12 SCLK falling edges (Figure 6). SSTRB
12
and DOUT go into a high-impedance state when CS goes high; after the next CS falling edge, SSTRB outputs a logic-low. Figure 8 shows the SSTRB timing in external clock mode. The conversion must complete in some minimum time, or droop on the sample-and-hold capacitors may degrade conversion results. Use internal clock mode if the serialclock frequency is less than 100kHz, or if serial-clock interruptions could cause the conversion interval to exceed 120Fs.
_____________________________________________________________________________________
+2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs MAX148/MAX149
CS
SCLK DIN SSTRB
1
2
3
4
5
6
7
8
9
10
11
12
18
19
20
21
22
23
24
SEL2 SEL1 SEL0 UNI/ SGL/ PD1 PD0 BIP DIF START tCONV
DOUT ACQUISITION 1.5Fs CONVERSION 7.5Fs MAX
B9 MSB B8 IDLE IDLE
B7
B0 LSB S1
FILLED WITH S0 ZEROS
AD STATE
(fSCLK = 2MHz)(SHDN = UNCONNECTED)
Figure 9. Internal Clock Mode Timing
CS tCSH SSTRB tSSTRB SCLK
tCONV tSCK
tCSS
PD0 CLOCK IN DOUT NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
tD0
Figure 10. Internal Clock Mode SSTRB Detailed Timing
Internal Clock In internal clock mode, the MAX148/MAX149 generate their own conversion clocks internally. This frees the FP from the burden of running the SAR conversion clock and allows the conversion results to be read back at the processor's convenience, at any clock rate from 0 to 2MHz. SSTRB goes low at the start of the conversion and then goes high when the conversion is complete. SSTRB is low for a maximum of 7.5Fs (SHDN = unconnected), during which time SCLK should remain low for best noise performance. An internal register stores data when the conversion is in progress. SCLK clocks the data out of this register at any time after the conversion is complete. After SSTRB goes high, the next falling clock edge produces the MSB of the conversion at DOUT, followed by the remaining bits in MSB-first format (Figure 9). CS does
not need to be held low once a conversion is started. Pulling CS high prevents data from being clocked into the MAX148/MAX149 and three-states DOUT, but it does not adversely affect an internal clock mode conversion already in progress. When internal clock mode is selected, SSTRB does not go into a high-impedance state when CS goes high. Figure 10 shows the SSTRB timing in internal clock mode. In this mode, data can be shifted in and out of the MAX148/MAX149 at clock rates exceeding 2.0MHz if the minimum acquisition time (tACQ) is kept above 1.5Fs. The falling edge of CS does not start a conversion. The first logic high clocked into DIN is interpreted as a start bit and defines the first bit of the control byte. A conversion starts on SCLK's falling edge, after the eighth bit of
13
Data Framing
______________________________________________________________________________________
+2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs MAX148/MAX149
Table 4. Typical Power-Up Delay Times
REFERENCE BUFFER Enabled Enabled Enabled Enabled Disabled Disabled REFERENCEBUFFER COMPENSATION MODE Internal Internal External External -- -- VREF CAPACITOR (F) -- -- 4.7 4.7 -- -- POWER-DOWN MODE Fast Full Fast Full Fast Full POWER-UP DELAY (s) 5 300 See Figure 14c See Figure 14c 2 2 MAXIMUM SAMPLING RATE (ksps) 26 26 133 133 133 133
the control byte (the PD0 bit) is clocked into DIN. The start bit is defined as follows: The first high bit clocked into DIN with CS low any time the converter is idle; e.g., after VDD is applied. OR The first high bit clocked into DIN after bit 3 of a conversion in progress is clocked onto the DOUT pin. If CS is toggled before the current conversion is complete, the next high bit clocked into DIN is recognized as a start bit; the current conversion is terminated, and a new one is started. The fastest the MAX148/MAX149 can run with CS held low between conversions is 15 clocks per conversion. Figure 11a shows the serial-interface timing necessary to perform a conversion every 15 SCLK cycles in external clock mode. If CS is tied low and SCLK is continuous, guarantee a start bit by first clocking in 16 zeros. Most microcontrollers (FCs) require that conversions occur in multiples of 8 SCLK clocks; 16 clocks per conversion is typically the fastest that a FC can drive the MAX148/MAX149. Figure 11b shows the serialinterface timing necessary to perform a conversion every 16 SCLK cycles in external clock mode.
Reference-Buffer Compensation In addition to its shutdown function, SHDN selects internal or external compensation. The compensation affects both power-up time and maximum conversion speed. The 100kHz minimum clock rate is limited by droop on the sample-and-hold and is independent of the compensation used. Unconnect SHDN to select external compensation. The Typical Operating Circuit uses a 4.7FF capacitor at VREF. A 4.7FF value ensures reference-buffer stability and allows converter operation at the 2MHz full clock speed. External compensation increases power-up time (see the Choosing Power-Down Mode section and Table 4). Pull SHDN high to select internal compensation. Internal compensation requires no external capacitor at VREF and allows for the shortest power-up times. The maximum clock rate is 2MHz in internal clock mode and 400kHz in external clock mode. You can save power by placing the converter in a lowcurrent shutdown state between conversions. Select full power-down mode or fast power-down mode via bits 1 and 0 of the DIN control byte with SHDN high or unconnected (Tables 1 and 5). In both software power-down modes, the serial interface remains operational, but the ADC does not convert. Pull SHDN low at any time to shut down the converter completely. SHDN overrides bits 1 and 0 of the control byte. Full power-down mode turns off all chip functions that draw quiescent current, reducing supply current to 2FA (typ). Fast power-down mode turns off all circuitry except the bandgap reference. With fast power-down mode, the supply current is 30FA. Power-up time can be shortened to 5Fs in internal compensation mode. Table 4 shows how the choice of reference-buffer compensation and power-down mode affects both power-up
Choosing Power-Down Mode
Applications Information
When power is first applied, and if SHDN is not pulled low, internal power-on reset circuitry activates the MAX148/MAX149 in internal clock mode, ready to convert with SSTRB = high. After the power supplies stabilize, the internal reset time is 10Fs, and no conversions should be performed during this phase. SSTRB is high on power-up and, if CS is low, the first logical 1 on DIN is interpreted as a start bit. Until a conversion takes place, DOUT shifts out zeros. Also see Table 4.
14
Power-On Reset
_____________________________________________________________________________________
+2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs MAX148/MAX149
CS 1 SCLK 8 15 1 8 15 1
DIN
S
CONTROL BYTE 0
S
CONTROL BYTE 1
S
CONTROL BYTE 2
DOUT
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0 CONVERSION RESULT 0
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0 CONVERSION RESULT 1
SSTRB
Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing
CS 1 SCLK DIN DOUT S CONTROL BYTE 0 B9 B8 B7 B6 B5 B4 B3 B2 S B1 B0 CONTROL BYTE 1 S1 S0 B9 B8 B7 B6 8 16 1 8 16
CONVERSION RESULT 0
CONVERSION RESULT 1
Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing
CLOCK MODE SHDN SETS EXTERNAL CLOCK MODE DIN SXXXXX11
EXTERNAL
EXTERNAL
SETS SOFTWARE POWER-DOWN SXXXXX00
SETS EXTERNAL CLOCK MODE SXX XXX1 1
DOUT
10 + 2 DATA BITS
10 + 2 DATA BITS
VALID DATA
INVALID DATA HARDWARE POWER-DOWN
MODE
POWERED UP SOFTWARE POWER-DOWN
POWERED UP
POWERED UP
Figure 12a. Timing Diagram Power-Down Modes, External Clock
delay and maximum sample rate. In external compensation mode, power-up time is 20ms with a 4.7FF compensation capacitor when the capacitor is initially fully discharged. From fast power-down, startup time can be eliminated by using low-leakage capacitors that do not
discharge more than 1/2 LSB while shut down. In powerdown, leakage currents at VREF cause droop on the reference bypass capacitor. Figures 12a and 12b show the various power-down sequences in both external and internal clock modes.
15
______________________________________________________________________________________
+2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs MAX148/MAX149
CLOCK MODE INTERNAL SETS INTERNAL CLOCK MODE SXXXXX10 5XXXXX00 SETS POWER-DOWN S
DIN
DOUT SSTRB CONVERSION MODE
DATA VALID
DATA VALID
CONVERSION POWERED OFF POWER-DOWN
POWERED UP
Figure 12b. Timing Diagram Power-Down Modes, Internal Clock
Table 5. Software Power-Down and Clock Mode
PD1 0 0 1 1 PD0 0 1 0 1 DEVICE MODE Full Power-Down Fast Power-Down Internal Clock External Clock
Table 6. Hard-Wired Power-Down and Internal Clock Frequency
SHDN STATE 1 Unconnected 0 DEVICE MODE Enabled Enabled PowerDown REFERENCE BUFFER COMPENSATION Internal External -- INTERNAL CLOCK FREQUENCY 225kHz 1.8MHz --
AVERAGE SUPPLY CURRENT vs. CONVERSION RATE WITH EXTERNAL REFERENCE
MAX148/9-F13
AVERAGE SUPPLY CURRENT vs. CONVERSION RATE (USING FULLPD)
RLOAD = CODE = 1010101000 8 CHANNELS
MAX148/9-F14A
10,000 AVERAGE SUPPLY CURRENT (A) 1000 100
100 AVERAGE SUPPLY CURRENT (A)
VREF = VDD = 3.0V RLOAD = CODE = 1010101000
8 CHANNELS
10
10
1 CHANNEL
1 0.1 0.1 1 10 100 1k 10k 100k 1M CONVERSION RATE (Hz)
1 CHANNEL
1 0.01 0.1 1 10 100 1k CONVERSION RATE (Hz)
Figure 13. Average Supply Current vs. Conversion Rate with External Reference 16
Figure 14a. MAX149 Supply Current vs. Conversion Rate, FULLPD
_____________________________________________________________________________________
+2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs
AVERAGE SUPPLY CURRENT vs. CONVERSION RATE (USING FASTPD)
RLOAD = CODE = 1010101000
1000
MAX148/9-F14B
10,000 AVERAGE SUPPLY CURRENT (A)
The first logical 1 on DIN is interpreted as a start bit and powers up the MAX148/MAX149. Following the start bit, the data input word or control byte also determines clock mode and power-down states. For example, if the DIN word contains PD1 = 1, then the chip remains powered up. If PD0 = PD1 = 0, a power-down resumes after one conversion. Hardware Power-Down Pulling SHDN low places the converter in hardware power-down (Table 6). Unlike software power-down mode, the conversion is not completed; it stops coincidentally with SHDN being brought low. SHDN also controls the clock frequency in internal clock mode. Leaving SHDN unconnected sets the internal clock frequency to 1.8MHz. When returning to normal operation with SHDN unconnected, there is a tRC delay of approximately 2MI x CL, where CL is the capacitive loading on the SHDN pin. Pulling SHDN high sets internal clock frequency to 225kHz. This feature eases the settling-time requirement for the reference voltage. With an external reference, the MAX148/MAX149 can be considered fully powered up within 2Fs of actively pulling SHDN high. The MAX148/MAX149 auto power-down modes can save considerable power when operating at less than maximum sample rates. Figures 13, 14a, and 14b show the average supply current as a function of the sampling rate. The following discussion illustrates the various power-down sequences. Lowest Power at Up to 500 Conversions/Channel/Second The following examples show two different power-down sequences. Other combinations of clock rates, compensation modes, and power-down modes may give lowest power consumption in other applications. Figure 14a depicts the MAX149 power consumption for one or eight channel conversions utilizing full powerdown mode and internal-reference compensation. A 0.01FF bypass capacitor at REFADJ forms an RC filter with the internal 20kI reference resistor with a 0.2ms time constant. To achieve full 10-bit accuracy, 8 time constants or 1.6ms are required after power-up. Waiting this 1.6ms in FASTPD mode instead of in full power-up can reduce power consumption by a factor of 10 or more. This is achieved by using the sequence shown in Figure 15.
MAX148/MAX149
8 CHANNELS
100
1 CHANNEL
0
1 0.1 1 10 100 1k 10k 100k 1M CONVERSION RATE (Hz)
Figure 14b. MAX149 Supply Current vs. Conversion Rate, FASTPD
TYPICAL REFERENCE-BUFFER POWER-UP DELAY vs. TIME IN SHUTDOWN
MAX148/9-F14C
2.0
Power-Down Sequencing
POWER-UP DELAY (ms)
1.5
1.0
0.5
0 0.001
0.01
0.1
1
10
TIME IN SHUTDOWN (s)
Figure 14c. Typical Reference-Buffer Power-Up Delay vs. Time in Shutdown
Software Power-Down Software power-down is activated using bits PD1 and PD0 of the control byte. As shown in Table 5, PD1 and PD0 also specify the clock mode. When software shutdown is asserted, the ADC operates in the last specified clock mode until the conversion is complete. Then the ADC powers down into a low quiescent-current state. In internal clock mode, the interface remains active and conversion results may be clocked out after the MAX148/MAX149 enter a software power-down.
______________________________________________________________________________________
17
+2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs MAX148/MAX149
COMPLETE CONVERSION SEQUENCE 1.6ms WAIT DIN 1 FULLPD 1.21V REFADJ 0 2.50V VREF 0 tBUFFEN = 75Fs H = RC = 20kI x CREFADJ 00 (ZEROS) 1 FASTPD 01 1 NOPD CH1 11 1 FULLPD CH7 00 (ZEROS) 1 FASTPD 01
Figure 15. MAX149 FULLPD/FASTPD Power-Up Sequence
+3.3V 24kI 510kI 100kI 0.01F 12
OUTPUT CODE 11...111 11...110 11...101 TRANSITION FULL-SCALE TRANSITION
MAX149
REFADJ
FS = VREF + COM ZS = COM
Figure 16. MAX149 Reference-Adjust Circuit
00...011
1 LSB =
VREF 1024
Lowest Power at Higher Throughputs Figure 14b shows the power consumption with externalreference compensation in fast power-down, with one and eight channels converted. The external 4.7FF compensation requires a 75Fs wait after power-up with one dummy conversion. This graph shows fast multichannel conversion with the lowest power consumption possible. Full power-down mode may provide increased power savings in applications where the MAX148/MAX149 are inactive for long periods of time, but where intermittent bursts of high-speed conversions are required. The MAX149 can be used with an internal or external reference voltage, whereas an external reference is required for the MAX148. An external reference can be connected directly at VREF or at the REFADJ pin. An internal buffer is designed to provide 2.5V at VREF for both the MAX149 and the MAX148. The MAX149's internally trimmed 1.21V reference is buffered with a 2.06 gain. The MAX148's REFADJ pin is also buffered with a 2.00 gain to scale an external 1.25V reference at REFADJ to 2.5V at VREF.
00...010 00...001 00...000 0 (COM) 1 2 3 INPUT VOLTAGE (LSB) FS - 3/2 LSB FS
Figure 17. Unipolar Transfer Function, Full Scale (FS) = VREF + COM, Zero Scale (ZS) = COM
Internal and External References
Internal Reference (MAX149) The MAX149's full-scale range with the internal reference is 2.5V with unipolar inputs and Q1.25V with bipolar inputs. The internal reference voltage is adjustable to Q1.5% with the circuit in Figure 16. External Reference With both the MAX149 and MAX148, an external reference can be placed at either the input (REFADJ) or the output (VREF) of the internal reference-buffer amplifier. The REFADJ input impedance is typically 20kI for the MAX149, and higher than 100kI for the MAX148. At VREF, the DC input resistance is a minimum of 18kI. During conversion, an external reference at VREF must
18
_____________________________________________________________________________________
+2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs
Table 7. Full Scale and Zero Scale
UNIPOLAR MODE Full Scale VREF + COM Zero Scale COM Positive Full Scale VREF/2 + COM BIPOLAR MODE Zero Scale COM Negative Full Scale -VREF/2 + COM
MAX148/MAX149
OUTPUT CODE FS = VREF + COM 2
011 . . . 111 011 . . . 110
ZS = COM -FS = -VREF + COM 2 VREF 1024
SUPPLIES +3V +3V GND
000 . . . 010 000 . . . 001 000 . . . 000 111 . . . 111 111 . . . 110 111 . . . 101
1LSB =
R* = 10
VDD
AGND
COM
DGND
+3V
DGND
100 . . . 001 100 . . . 000 - FS COM* INPUT VOLTAGE (LSB) *COM VREF/2 +FS - 1LSB
MAX148 MAX149 *OPTIONAL
DIGITAL CIRCUITRY
Figure 18. Bipolar Transfer Function, Full Scale (FS) = VREF/2 + COM, Zero Scale (ZS) = COM
Figure 19. Power-Supply Grounding Connection
deliver up to 350FA DC load current and have 10I or less output impedance. If the reference has a higher output impedance or is noisy, bypass it close to the VREF pin with a 4.7FF capacitor. Using the REFADJ input makes buffering the external reference unnecessary. To use the direct VREF input, disable the internal buffer by tying REFADJ to VDD. In power-down, the input bias current to REFADJ is typically 25FA (MAX149) with REFADJ tied to VDD. Pull REFADJ to AGND to minimize the input bias current in power-down.
Table 7 shows the full-scale voltage ranges for unipolar and bipolar modes.
Transfer Function
The external reference must have a temperature coefficient of 20ppm/NC or less to achieve accuracy to within 1 LSB over the 0NC to +70NC commercial temperature range. Figure 17 depicts the nominal, unipolar input/output (I/O) transfer function, and Figure 18 shows the bipolar input/output transfer function. Code transitions occur halfway between successive-integer LSB values. Output coding is binary, with 1 LSB = 2.44mV (2.500V/1024) for unipolar operation, and 1 LSB = 2.44mV [(2.500V/2 -2.500V/2)/1024] for bipolar operation.
______________________________________________________________________________________
19
+2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs MAX148/MAX149
+3V +3V
0.1F 1 2 3 ANALOG INPUTS 4 5 6 7 8 9 10 CH0 CH1 CH2 MAX148 MAX149 CH3 CH4 CH5 CH6 CH7 COM SHDN VDD SCLK CS DIN SSTRB DOUT DGND AGND REFADJ VREF 20 19 18 17 16 15 14 13 12 11 0.1F +2.5V
1F (POWER SUPPLIES) SCK PCS0 MOSI
MC683XX
MISO
(GND)
Figure 20. MAX148/MAX149 QSPI Connections, External Reference
XF CLKX
CS SCLK MAX148 MAX149 DIN DOUT SSTRB
TMS320LC3x
CLKR DX DR FSR
For best performance, use PCBs. Wire-wrap boards are not recommended. Board layout should ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) lines parallel to one another, or digital lines underneath the ADC package. Figure 19 shows the recommended system ground connections. Establish a single-point analog ground (star ground point) at AGND, separate from the logic ground. Connect all other analog grounds and DGND to the star ground. No other digital system ground should be connected to this ground. For lowest-noise operation, the ground return to the star ground's power supply should be low impedance and as short as possible. High-frequency noise in the VDD power supply may affect the high-speed comparator in the ADC. Bypass the supply to the star ground with 0.1FF and 1FF capacitors close to pin 20 of the MAX148/MAX149. Minimize capacitor lead lengths for best supply-noise rejection. If the power supply is very noisy, a 10I resistor can be connected as a lowpass filter (Figure 19).
Layout, Grounding, and Bypassing
Figure 21. MAX148/MAX149-to-TMS320 Serial Interface
20
_____________________________________________________________________________________
8-string WLED Driver with Integrated Step-up Regulator and SMBus/PWM Dimming Capability MAX148/MAX149
CS
SCLK
DIN
START
SEL2
SEL1
SEL0
UNI/BIP
SGL/DIF
PD1
PD0
SSTRB
HIGH IMPEDANCE HIGH IMPEDANCE
DOUT
MSB
B8
S1
S0
Figure 22. TMS320 Serial-Interface Timing Diagram
The MAX148/MAX149 can interface with QSPI using the circuit in Figure 20 (fSCLK = 2.0MHz, CPOL = 0, CPHA = 0). This QSPI circuit can be programmed to do a conversion on each of the eight channels. The result is stored in memory without taxing the CPU, since QSPI incorporates its own microsequencer.
High-Speed Digital Interfacing with QSPI
2) The MAX148/MAX149's CS pin is driven low by the TMS320's XF_ I/O port to enable data to be clocked into the MAX148/MAX149's DIN. 3) An 8-bit word (1XXXXX11) should be written to the MAX148/MAX149 to initiate a conversion and place the device into external clock mode. See Table 1 to select the proper XXXXX bit values for your specific application. 4) The MAX148/MAX149's SSTRB output is monitored through the TMS320's FSR input. A falling edge on the SSTRB output indicates that the conversion is in progress and data is ready to be received from the MAX148/MAX149. 5) The TMS320 reads in one data bit on each of the next 16 rising edges of SCLK. These data bits represent the 10 + 2-bit conversion result followed by 4 trailing bits, which should be ignored. 6) Pull CS high to disable the MAX148/MAX149 until the next conversion is initiated.
The MAX148/MAX149 are QSPI compatible up to the maximum external clock frequency of 2MHz. Figure 21 shows an application circuit to interface the MAX148/MAX149 to the TMS320 in external clock mode. The timing diagram for this interface circuit is shown in Figure 22.
TMS320LC3x Interface
Use the following steps to initiate a conversion in the MAX148/MAX149 and to read the results: 1) The TMS320 should be configured with CLKX (transmit clock) as an active-high output clock and CLKR (TMS320 receive clock) as an active-high input clock. CLKX and CLKR on the TMS320 are tied together with the MAX148/MAX149's SCLK input.
______________________________________________________________________________________
21
+2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs MAX148/MAX149
Ordering Information (continued)
PART MAX148AEPP MAX148BEPP MAX148AEAP MAX148BEAP MAX148AMJP MAX148BMJP MAX149ACPP MAX149BCPP MAX149ACAP MAX149BCAP MAX149AEPP MAX149BEPP MAX149AEAP MAX149BEAP MAX149AMJP MAX149BMAP/PR MAX149BMJP TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -55C to +125C 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -55C to +125C -55C to +125C PINPACKAGE 20 Plastic DIP 20 Plastic DIP 20 SSOP 20 SSOP 20 CERDIP* 20 CERDIP* 20 Plastic DIP 20 Plastic DIP 20 SSOP 20 Plastic DIP 20 Plastic DIP 20 Plastic DIP 20 SSOP 20 SSOP 20 CERDIP* 20 SSOP 20 CERDIP* INL (LSB) 1/2 1 1/2 1 1/2 1 1/2 1 1/2 1 1/2 1 1/2 1 1/2 1 1
TOP VIEW CHO CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM 1 2 3 4 5 6 7 8 9 11 VDD 12 SCLK 13 CS
Pin Configuration
MAX148 MAX149
14 DIN 15 SSTRB 16 DOUT 17 DGND 18 AGND 19 REFADJ 20 VREF
SHDN 10
DIP/SSOP
Contact factory for availability of alternate surface-mount package. Specify lead-free by placing + by the part number when ordering. *Contact factory for availability of CERDIP package, and for processing to MIL-STD-883B. Not available in lead-free.
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 20 Plastic Dip 20 SSOP 20 CERDIP PACKAGE CODE P20-4 A20-1 J20-2 DOCUMENT NO. 21-0043 21-0056 21-0045
22
_____________________________________________________________________________________
+2.7V to +5.25V, Low-Power, 8-Channel, Serial 10-Bit ADCs
Revision History
REVISION NUMBER 3 REVISION DATE 5/09 DESCRIPTION Revised Ordering Information, Electrical Characteristics table, Pin Description, Figure 9, added ruggedized plastic information. PAGES CHANGED 1-4, 7, 13, 14, 16, 17, 22-23
MAX148/MAX149
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
(c)
23
2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.

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